ขาย Text Book : Computer Organization and Architecture: International Version: Designing for Performance

 Covers fundamentals such as CPU, control unit, microprogramming, instruction set, I/O,    and memory. Also covers advanced topics such as RISC, superscalar, and parallel organization   Table of content Chapter 1 Introduction  1.1 Organization and Architecture 
1.2 Structure and Function 
1.3 Key Terms and Review Questions  Chapter 2 Computer Evolution and Performance
2.1 A Brief History of Computers 
2.2 Designing for Performance 
2.3 Multicore, MICs, and GPGPUs 
2.4 The Evolution of the Intel x86 Architecture 
2.5 Embedded Systems and the Arm 
2.6 Performance Assessment 
2.7 Recommended Reading 
2.8 Key Terms, Review Questions, and Problems  Part Two The Computer System  Chapter 3 A Top-Level View of Computer Function and Interconnection 
3.1 Computer Components 
3.2 Computer Function 
3.3 Interconnection Structures 
3.4 Bus Interconnection 
3.5 Point-To-Point Interconnect
3.6 PCI Express 
3.7 Recommended Reading 
3.8 Key Terms, Review Questions, and Problems  Chapter 4 Cache Memory 
4.1 Computer Memory System Overview 
4.2 Cache Memory Principles 
4.3 Elements of Cache Design
4.5 Arm Cache Organization 
4.6 Recommended Reading 
4.7 Key Terms, Review Questions, and Problems  Appendix 4A Performance Characteristics of Two-Level Memories  Chapter 5 Internal Memory 
5.1 Semiconductor Main Memory
5.2 Error Correction 
5.3 Advanced Dram Organization
5.4 Recommended Reading 
5.5 Key Terms, Review Questions, and Problems  Chapter 6 External Memory 
6.1 Magnetic Disk 
6.2 Raid 
6.3 Solid State Drives 
6.4 Optical Memory 
6.5 Magnetic Tape 
6.6 Recommended Reading 
6.7 Key Terms, Review Questions, and Problems  Chapter 7 Input/Output 
7.1 External Devices 
7.2 I/O Modules 
7.3 Programmed I/O 
7.4 Interrupt-Driven I/O 
7.5 Direct Memory Access 
7.6 I/O Channels and Processors 
7.7 The External Interface: Thunderbolt and Infiniband 
7.8 IBM zEnterprise 196 I/O Structure 
7.9 Recommended Reading 
7.10 Key Terms, Review Questions, and Problems  Chapter 8 Operating System Support 
8.1 Operating System Overview 
8.2 Scheduling 
8.3 Memory Management 
8.4 Pentium Memory Management 
8.5 ARM Memory Management 
8.6 Recommended Reading 
8.7 Key Terms, Review Questions, and Problems  Part three Arithmetic and Logic  Chapter 9 Number Systems 
9.1 The Decimal System 
9.2 Positional Number Systems 
9.3 The Binary System 
9.4 Converting Between Binary and Decimal 
9.5 Hexadecimal Notation 
9.6 Recommended Reading 
9.7 Key Terms and Problems  Chapter 10 Computer Arithmetic 
10.1 The Arithmetic and Logic Unit 
10.2 Integer Representation 
10.3 Integer Arithmetic 
10.4 Floating-Point Representation 
10.5 Floating-Point Arithmetic 
10.6 Recommended Reading 
10.7 Key Terms, Review Questions, and Problems  Chapter 11 Digital Logic 
11.1 Boolean Algebra 
11.2 Gates 
1.3 Combinational Circuits 
11.4 Sequential Circuits
11.5 Programmable Logic Devices 
11.6 Recommended Reading 
11.7 Key Terms and Problems  Part Four The Central Processing Unit  Chapter
12 Instruction Sets: Characteristics and Functions 
12.1 Machine Instruction Characteristics 
12.2 Types of Operands 
12.3 Intel x86 and Arm Data Types 
12.4 Types of Operations 
12.5 Intel x86 and ARM Operation Types
12.6 Recommended Reading 
12.7 Key Terms, Review Questions, and Problems  Appendix
12A Little-, Big-, and Bi-Endian  Chapter 13 Instruction Sets: Addressing Modes and Formats 
13.1 Addressing Modes  13.2 x86 and ARM Addressing Modes 
13.3 Instruction Formats  13.4 x86 and ARM Instruction Formats 
13.5 Assembly Language  13.6 Recommended Reading 
13.7 Key Terms, Review Questions, and Problems  Chapter 14 Processor Structure and Function 
14.1 Processor Organization  14.2 Register Organization  
14.3 Instruction Cycle  14.4 Instruction Pipelining 
14.5 The x86 Processor Family  14.6 The Arm Processor 520
14.7 Recommended Reading 526 14.8 Key Terms, Review Questions, and Problems  Chapter 15 Reduced Instruction Set Computers
15.1 Instruction Execution Characteristics 
15.2 The Use of a Large Register File 
15.3 Compiler-Based Register Optimization 
15.4 Reduced Instruction Set Architecture 
15.5 RISC Pipelining  15.6 MIPS R4000 
15.7 Sparc 5 15.8 RISC Versus CISC Controversy 
15.9 Recommended Reading  15.10 Key Terms, Review Questions, and Problems  Chapter 16 Instruction-Level Parallelism and Superscalar Processors 
16.1 Overview  16.2 Design Issues 
16.3 Pentium 4 16.4 Arm Cortex-A8 
16.5 Recommended Reading 6
16.6 Key Terms, Review Questions, and Problems 605 Part Five Parallel Organization  Chapter 17 Parallel Processing 
17.1 Multiple Processor Organizations 
17.2 Symmetric Multiprocessors 
17.3 Cache Coherence and the MESI Protocol 
17.4 Multithreading and Chip Multiprocessors 
17.5 Clusters  17.6 Nonuniform Memory Access
17.7 Vector Computation  17.8 Recommended Reading 
17.9 Key Terms, Review Questions, and Problems 
18.1 Hardware Performance Issues 
18.2 Software Performance Issues 
18.3 Multicore Organization 
18.4 Intel x86 Multicore Organization 
18.5 ARM11 MPCore